There has been a demand for lower resistance of wiring in order to perform a high-speed operation of semiconductor elements. It is however undesirable to thicken a wiring formed under design rules (line and space) to lower the resistance of the wiring because the thick wiring increases a wiring-to-wiring capacitance. In general, the decrease in wiring resistance and the reduction in wiring-to-wiring capacitance are contradictory to each other.
A damascene technique is known as a new wiring forming method. In this technique, an insulation film is formed, and a wiring trench is formed in the insulation film and then filled with wiring materials (e.g., metallic materials such as aluminum). A planarization method such as CMP (Chemical Mechanical Polishing) is employed for filling the wiring trench with the wiring materials.
A conventional wiring forming method using a dual damascene technique which is an improvement of the damascene technique, will now be described with reference to FIGS. 12A to 12D.
Referring first to FIG. 12A, a lower wiring layer 203 is formed on a silicon (Si) substrate 201 with an interlayer insulation film 202 therebetween, and a flat interlayer insulation film 204 (SiO2 film) is formed on the lower wiring layer 203. A wiring trench 205 (whose depth is for example 0.5 xcexcm) is then formed in the SiO2 film 204.
Referring then to FIG. 12B, resist is applied onto the entire surface of the resultant structure and exposed by lithography to form a resist pattern 206 for forming a contact hole. Using this resist pattern 206 as a mask, its underlying SiO2 film 204 is etched to form a contact hole 207 therein.
As shown in FIG. 12C, the resist pattern 206 is exfoliated and then a metal film 208, which is to serves as wiring, is deposited on the whole surface so as to fill both the wiring trench 205 and contact hole 207.
Finally, as illustrated in FIG. 12D, an unnecessary portion of the metal film 208, which exists outside the wiring trench 205 and contact hole 207, is eliminated by CMP.
Consequently, a wiring structure (dual damascene structure) is completed in which both the wiring trench 205 and contact hole 207 are filled with the metal film (wiring) 208.
FIG. 13 shows a lengthwise cross section of the wiring 208 formed by the dual damascene method. Though contact portions 209 of the wiring are also filled with wiring materials, a wiring portion thereof (excluding the contact portions 209) has a uniform thickness.
Even in the wiring forming technique using the dual damascene method, it is difficult to decrease in both wiring resistance and wiring-to-wiring capacitance at the same time. More specifically, the wiring thickness depends upon a relationship between wiring-to-wiring capacitance and wiring resistance at the minimum pitch in which an increase of the wiring-to-wiring resistance is a serious problem, and it is difficult to lower the wiring resistance while preventing the wiring-to-wiring capacitance from increasing when the wiring is more miniaturized by higher degree of integration.
As one method of resolving the above problem, a wiring structure having different wiring depths and its manufacturing method are proposed (Jpn. Pat. Appln. KOKAI Publication No. 9-321046). This method will now be described in brief with reference to FIGS. 14A to 14D.
First, as illustrated in FIG. 14A, an interlayer insulation film 222 is formed on a silicon substrate 221, a lower wiring layer 223 is formed on the film 222, and another interlayer insulation film 224 is formed on the film 222 and layer 223. Trenches 226, 227 and 228 are then formed in the interlayer insulation film 224 using a resist pattern 225 as a mask.
As shown in FIG. 14B, using a resist pattern 229 as a mask, the interlayer insulation film 224 is etched to form a contact hole 230 and wiring trenches 231 and 232.
As shown in FIG. 14C, a metal film 233 serving as wiring is formed on the entire surface of the resultant structure so as to fill the contact hole 230 and wiring trenches 231 and 232.
Finally, as illustrated in FIG. 14D, an unnecessary portion of the metal film 233, which exists outside the contact hole 230 and wiring trenches 231 and 232, is eliminated, thus completing wirings 235 to 238. The wiring 235 is connected to the lower wiring layer 223 through a contact portion 234.
According to the conventional method depicted in FIGS. 14A to 14D, the wirings 235 to 238 having different thicknesses are formed in the same layer, but each wiring has a uniform thickness. The inventors of the present invention do not therefore believe that the conventional method is sufficient for enhancing a degree of flexibility in wiring. In other words, they think it difficult to lower the wiring resistance and reduce the wiring-to-wiring capacitance.
The present invention has been developed to solve the above problem, and its object is to provide a semiconductor device capable of decreasing in both wiring resistance and wiring-to-wiring capacitance at the same time and a method for manufacturing the same.
A semiconductor device according to a first aspect of the present invention comprises a first conductive section formed in a first layer on a semiconductor substrate, and a second conductive section formed in a second layer on the semiconductor substrate and including a connection region connected to the first conductive section and at least one conductive region which varies in thickness.
More specifically, the above semiconductor device has the following structures:
(1) The first conductive section is a wiring or a diffusion layer, and the second conductive section is a wiring. The wiring of the second conductive section is formed above the wiring or diffusion layer of the first conductive section or under the wiring of the first conductive section.
(2) The wiring includes a conductive region which becomes narrower and thicker toward the semiconductor substrate. More specifically, the wiring includes a conductive region which becomes narrower and thicker discontinuously or continuously toward the semiconductor substrate.
(3) An element is formed under a region other than a thickest conductive region of the wiring.
(4) A gate electrode is formed under a region other than a thickest conductive region of the wiring.
According to the present invention, the plural regions having different thicknesses can be arranged properly in a single continuous wiring in relation to its surrounding wirings. The wiring resistance can thus be decreased and so can be the wiring-to-wiring capacitance.
The reason why the regions having different thicknesses are formed in the same wiring in the wiring region excluding the connection region connected to the conductive region, are as follows. The connection region includes a conductive region for connecting the upper and lower wirings and differs in thickness from the original wiring section (the former is thicker than the latter). Such a connection region is therefore excluded from the wiring region of the present invention.
A semiconductor device according to a second aspect of the present invention comprises a first wiring formed on a semiconductor substrate and including a thick region and a thin region, and a second wiring formed adjacent to the first wiring in a same layer as that of the first wiring on the semiconductor substrate and including a thick region and a thin region, wherein the thick region of the first wiring and a thin region of the second wiring are at least partly opposed to each other.
More specifically, the above semiconductor device has the following structures:
(1) The thin region of the first wiring is opposed only to the thick region of the second wiring, and the thick region of the first wiring is opposed only to the thin region of the second wiring.
(2) The thin region of the first wiring is opposed to both the thick region and the thin region of the second wiring, and the thick region of the first wiring is opposed to both the thick region and the thin region of the second wiring.
In the above semiconductor device, the plural wirings are formed adjacent to each other in the same wiring layer and the thin and thick regions are arranged opposite to each other. The capacitance between the wirings can be reduced more effectively.
A semiconductor device according to a third aspect of the present invention 11 comprises a first wiring formed on a semiconductor substrate and having a uniform thickness, and a second wiring formed adjacent to the first wiring in a same layer as that of the first wiring on the semiconductor substrate and including a thick region and a thin region.
More specifically, the above semiconductor device has the following structures:
(1) The thickness of the first wiring is equal to that of the thin region of the second wiring.
Even when only one of adjacent two wirings in the same layer includes both thin and thick regions, if these regions are arranged properly in relation to the surrounding wirings, the wiring resistance can be decreased and the wiring-to-wiring capacitance can be reduced.
A method of manufacturing a semiconductor device according to a fourth aspect of the present invention comprises the steps of forming a first insulation film on a semiconductor substrate and then forming a second insulation film on the first insulation film, etching the second insulation film and then the first insulation film to form a first wiring trench in a multilayer film of the second insulation film and the first insulation film, covering part of the first wiring trench with mask materials, etching the first insulation film using the mask materials and the second insulation film as masks and deepening other part of the first wiring trench, which is not covered with the mask materials, to form a second wiring trench, which is deeper than the first wiring trench, in part of the multilayer film in which the first wiring trench is formed, and forming a wiring in the first wiring trench and the second wiring trench.
More specifically, the above method has the following features:
(1) The first insulation film is a silicon oxide film and the second insulation film is a silicon nitride film.
(2) The step of forming the wiring includes a step of removing the mask materials, a step of forming a conductive film as the wiring on an entire surface of the multilayer film so as to fill the first and second wiring trenches, and a step of removing the conductive film formed outside the first and second wiring trenches.
(3) The conductive film is removed by chemical mechanical polishing.
According to the foregoing method, the second wiring trench is formed by etching the first wiring trench further. In the normal lithography process, for example, the width of an opening pattern for the second wiring trench is set greater than that for the first wiring trench in consideration of out-of-mask-alignment caused between the first and second wiring trenches. As in the prior art of FIGS. 14A to 14D, the second wiring trench is formed in two steps, and width of the second wiring trench is wider than that of the first wiring trench. Consequently, it is thus difficult to enhance the density of the wiring.
Since, in the present invention, the second insulation film, which is subjected to patterning in the step of forming the first wiring trench, is used as an etching mask to form the second wiring trench, the width of the second wiring trench can be equal to that of the first wiring trench. Since, therefore, the width of the wiring can be fixed, an advantage of achieving a high-density wiring as well as that of decreasing both wiring resistance and wiring-to-wiring capacitance can be obtained.
A method of manufacturing a semiconductor device according to a fifth aspect of the present invention comprises the steps of forming a first insulation film on a semiconductor substrate and then forming a second insulation film on the first insulation film, etching the second insulation film and then the first insulation film to form a first wiring trench in a multilayer film of the second insulation film and the first insulation film, removing part of the second insulation film to expose part of the first insulation film, etching the first insulation film using the second insulation film as a mask to form a second wiring trench which is deeper than the first wiring trench and form a third wiring trench, which is shallower than the second wiring trench, in the exposed part of the first insulation film, and forming a wiring in the second and third wiring trenches.
This method has the same specific features as those of the above method.
Since, in this method, the second insulation film, which is subjected to patterning in the step of forming the first wiring trench, is used to form the second wiring trench, the width of the wiring can be fixed and the same advantage as the foregoing advantage can be obtained.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.